1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device including a gate electrode or source/drain regions obtained by control of diffusion and activation of impurities in polycrystalline semiconductor film, and a method for fabricating the same.
2. Description of the Related Art
Recently, CMOS transistors having a dual-gate structure have been developed. The dual-gate structure is provided to prevent variation of the threshold voltage of a transistor as well as the short channel effect. This structure includes two surface-channel transistors, one of which is an NMOS transistor having a gate electrode containing an n-type impurity and the other of which is a PMOS transistor having a gate electrode containing a P-type impurity.
Japanese Laid-Open Publication No. 6-224380 discloses a method for doping a gate electrode of a conventional dual-gate structure CMOS transistor with an impurity and activating the impurity in the doped gate electrode.- Specifically, as shown in FIG. 1, a pxe2x88x92-well 106, an nxe2x88x92-well 107, a field oxide film (element-isolating region) 102, and an inversion prevention layer 104 are provided on a semiconductor substrate 101 in a well-known way. A gate insulation film 105 (e.g., made of oxide film) is provided to cover those layers in a well-known way. A polycrystalline silicon film 103 to serve as a gate electrode is formed on the gate insulation film 105 with LPCVD. Thereafter, the polycrystalline silicon film 103 is patterned into the desired shape, and the source/drain regions and the gate electrode are doped with an impurity as a dopant by means of ion implantation. The resulting structure is then subjected to thermal treatment so as to activate the implanted dopant ions.
Japanese Laid-Open Publication No. 3-138930 discloses a transistor including a shallow junction which is provided in source/drain regions using a stacking structure for preventing the short channel effect which emerges as the transistor becomes smaller. FIG. 2 is a cross-sectional view showing diagrammatically a structure of the stacking-structure transistor disclosed the above-described publication.
In the conventional transistor having a structure as shown in FIG. 2, a gate electrode structure includes a gate insulating film 203, a gate electrode 204, and an insulating top layer 205. The gate electrode structure is provided over a region which will be a channel region between regions which will be source/drain regions 207. The gate electrode structure and those regions are positioned between field oxide films 202 (element-isolating regions) provided on a substrate 201. Sidewalls 211 are provided on the sides of the gate structure.
To form the source/drain regions 207 in this structure, a polycrystalline silicon film is provided to cover the gate electrode structure. Thereafter, the polycrystalline silicon film is etched back to a level indicated reference numeral 206 shown in FIG. 2. The polycrystalline silicon film 206 is doped with an impurity as a dopant and subjected to thermal treatment. The thermal treatment causes a solid phase diffusion so that the dopant diffuses from the polycrystalline silicon film 206 into the semiconductor substrate 201, thereby producing the source/drain regions 207.
After the formation of the source/drain regions 207, a silicide film 208 and an inactive dielectric layer 209 are formed over the polycrystalline silicon film 206, and a metal wire 210 is provided, resulting in the structure shown in FIG. 2.
However, when attempting to fabricate the conventional dual-gate-structure CMOS transistor using the surface-channel transistor, the following problems arise.
Phosphorous and arsenic as n-type impurities have a lower diffusion rate and a lower activation ratio in the polycrystalline silicon than Boron as a p-type impurity. For this reason, carriers are adversely depleted from the gate insulating film side of the gate electrode. The depletion layer of the gate electrode has a capacitance which is added in series to the capacitance of the gate insulating film, resulting in a reduction in effective capacitance. This reduces a driving current for the transistor. The driving current varies depending on the degree of depletion.
In general, impurity implantation is simultaneously carried out both for the gate electrode and the source/drain regions to be formed in order to reduce the number of steps in formation of the dual-gate-structure CMOS transistor. In this case, preferably, the source/drain function has a shallow junction so as to prevent the short channel effect of the transistor. To this end, reduced energy of ion implantation is preferable. This is, however, likely to deplete carriers from the gate electrode.
As described above, there is a trade-off between prevention of depletion in the gate electrode and prevention of the short channel effect. The prevention of the short channel effect leads to the depletion in the gate electrode. On the other hand, when the gate electrode is doped under conditions for preventing the depletion, the junction in the source/drain regions become deep, resulting in an increase in the short channel effect.
On the other hand, the short channel effect is increased as the size of the transistor is decreased. To prevent the short channel effect in this situation, the stacking-structure transistor has a shallow junction which is formed in the source/drain region using the stacking structure. When the source/drain regions are provided with the stacking structure using polycrystalline silicon film, the following problems arise.
To form as shallow a junction as possible, the amount of impurities implanted into the polycrystalline silicon film is preferably reduced so as to avoid the influence of extraordinary accelerated diffusion from a high-concentration region. The reduced amount of impurities of the source/drain regions does not cause the source/drain regions to have a sufficiently lowered level of resistance, resulting in an increase in parasitic resistance. This leads to a decrease in a transistor current in operation.
According to one aspect of the present invention, a method for fabricating a semiconductor device including a polycrystalline semiconductor film containing impurities, includes the steps of introducing the impurities into the polycrystalline semiconductor film; and subjecting the polycrystalline semiconductor film to thermal treatment in an oxidization atmosphere to carry out oxidization of the polycrystalline semiconductor film and activation of the impurities simultaneously.
According to another aspect of the present invention, a method for fabricating a semiconductor device including a polycrystalline semiconductor film containing impurities, includes the steps of depositing the polycrystalline semiconductor film; oxidizing the polycrystalline semiconductor film; introducing the impurities into the oxidized polycrystalline semiconductor film; and subjecting the oxidized polycrystalline semiconductor film to annealing to activating the impurities.
In one embodiment of this invention, the method for fabricating a semiconductor device includes the steps of: depositing an amorphous silicon film; and obtaining the polycrystalline silicon film by crystallizing the amorphous silicon film.
In one embodiment of this invention, the polycrystalline semiconductor film has a crystal defect density of about 1xc3x971018 cmxe2x88x923 or less.
In one embodiment of this invention, the polycrystalline semiconductor film is a polycrystalline silicon film.
In one embodiment of this invention, the impurities are phosphorous, boron, arsenic, or antimony.
According to another aspect of the present invention, a semiconductor device includes an insulating-gate field effect transistor structure having a gate electrode. The gate electrode includes a polycrystalline semiconductor film having a crystal defect density of about 1xc3x971018 cmxe2x88x923 or less.
In one embodiment of this invention, the gate electrode has a multilayer structure of the polycrystalline semiconductor film and a metal film or metal suicide film.
In one embodiment of this invention, the polycrystalline semiconductor film is a polycrystalline silicon film.
According to another aspect of the present invention, a semiconductor device includes an insulating-gate field effect transistor structure having source/drain regions stacked above a semiconductor substrate. The source/drain regions include a polycrystalline silicon film having a crystal defect density of about 1xc3x971018 cmxe2x88x923 or less.
In one embodiment of this invention, the source/drain regions have a multilayer structure of the polycrystalline semiconductor film and a metal film or metal silicide film.
In one embodiment of this invention, the polycrystalline semiconductor film is a polycrystalline silicon film.
According to another aspect of the present invention, a semiconductor device includes an insulating-gate field effect transistor structure having a gate electrode. The gate electrode includes a polycrystalline semiconductor film having an average crystal grain diameter of about 50 nm or more in the thickness direction.
According to another aspect of the present invention, a semiconductor device includes an insulating-gate field effect transistor structure having source/drain regions stacked above a semiconductor substrate. The source/drain regions have a polycrystalline semiconductor film having an average crystal grain diameter of about 50 nm or more in the thickness direction.
In one embodiment of this invention, the polycrystalline semiconductor film included in the gate electrode is a polycrystalline silicon film.
In one embodiment of this invention, the polycrystalline semiconductor film included in the source/drain regions is a polycrystalline silicon film.
According to this invention, in a semiconductor device including a polycrystalline semiconductor film containing impurities, the polycrystalline semiconductor film containing the impurities is formed by the step for introducing the impurities into the polycrystalline semiconductor film, and in the step for subjecting the polycrystalline semiconductor film to thermal treatment in an oxidization atmosphere to oxidize the polycrystalline semiconductor film, the impurities are activated. The oxidization atmosphere may be any atmosphere such as oxygen and water vapor which generates an oxidization reaction. The temperature of the oxidization is about 600xc2x0 C. to about 1200xc2x0 C. Since the polycrystalline semiconductor film is oxidized with the oxidization atmosphere during the activation of the impurities, the polycrystalline semiconductor film is recrystallized, thereby reducing the crystal defect density in the polycrystalline semiconductor film. For this reason, the amount of the impurities which are trapped by crystal defects and are not activated can be reduced, resulting in an increase in an activation ratio.
According to another aspect of this invention, impurities are introduced into an oxidized polycrystalline semiconductor film before the polycrystalline semiconductor film is subjected to annealing for activation of the impurities. This leads to recrystallization of the polycrystalline semiconductor film, thereby reducing the crystal defect density of the polycrystalline semiconductor film significantly. Only a reduced portion of impurities which are implanted into the polycrystalline semiconductor film in the later ion implantation is trapped by crystal defects. An increased activation ratio can be obtained after annealing for activation.
The polycrystalline semiconductor film may be, for example, polycrystalline silicon film. The crystal defect density of the polycrystalline silicon film is, for example, about 1xc3x971018 cmxe2x88x923 or less. The crystal defect density is smaller than the impurity amount by one order of magnitude or more, thereby sufficiently reducing the amount of impurities which are trapped by crystal defects and do not contribute to the activation.
The recrystallized polycrystalline semiconductor film is a polycrystalline film having an average crystal grain diameter of about 50 nm or more along the depth direction from the interface to the surface. The average crystal grain diameter is more preferably about 100 nm or more.
The polycrystalline semiconductor film may be, for example, polycrystalline silicon film. An average crystal grain diameter of the polycrystalline semiconductor film is about 50 nm or more, more preferably about 100 nm or more. The crystal defect density is therefore smaller than the impurity amount by one order of magnitude or more, thereby sufficiently reducing an amount of impurities which are trapped by crystal defects and do not contribute to the activation.
The above-described impurities may be phosphorous, boron, arsenic, or antimony. In particular, phosphorous has a high probability of being trapped by a defect in the polycrystalline silicon film. Therefore, reduction of crystal defects in the polycrystalline semiconductor film can increase the activation ratio significantly.
When the above-described polycrystalline semiconductor film is formed by the step for deposition of the amorphous silicon film and the step for crystallization of the amorphous silicon film, the resultant polycrystalline semiconductor film has a large crystal grain diameter. For this reason, the defect density in the film is decreased as compared with when direct deposition of the polycrystalline semiconductor film.
Further, when a gate electrode of an insulating-gate field effect transistor includes the above-described polycrystalline semiconductor film according to this invention, the following effects are obtained.
In general, to prevent depletion of a gate electrode, impurities having a concentration of about 1xc3x971019 cmxe2x88x923 or more are required. On the other hand, to control threshold voltage, a channel impurity concentration is preferably about 1xc3x971017 cmxe2x88x923 to about 3xc3x971017 cmxe2x88x923. In a typical ion implantation step, even when it is assumed that an impurity distribution is simply a Gaussian distribution, it is at a deep position about 4.3 "sgr" from the peak depth Rp (projected range) of the impurity distribution that the impurity concentration is decreased by about three orders of magnitude. To avoid depletion, ion implantation is generally carried out so as to provide a peak concentration of about 1xc3x971020 cmxe2x88x923. To prevent impurity ions from penetrating into the channel, however, the depth position about 4.3 "sgr" from the Rp should be within the polycrystalline silicon film included in the gate electrode. When this position is deeper than the thickness of the polycrystalline silicon film included in the gate electrode, the impurity ions reach the channel region. When the energy of ion implantation is set so that the depth position about 4.3 "sgr" from the Rp is within the polycrystalline silicon, such ion implantation causes a very shallow Rp. This makes it difficult to keep an impurity concentration of about 1xc3x971019 cmxe2x88x923 or more in the gate electrode (the polycrystalline silicon film) in the vicinity of the gate insulating film.
On the other hand, in this invention, the above-described polycrystalline silicon film having a high activation ratio is used as the gate electrode. This makes it easy to keep an impurity concentration of about 1xc3x971019 cmxe2x88x923 or more in the gate electrode (the polycrystalline silicon film) in the vicinity of the gate insulating film while preventing the impurity ions from penetrating into the channel region.
Furthermore, the gate electrode of the insulating-gate field effect transistor can include a multilayer film of the polycrystalline silicon film obtained by this invention and a metal film or metal silicide film, thereby obtaining a gate electrode having a further low resistivity.
The source/drain regions, which are stacked above the channel region in the insulating-gate field effect transistor, can include the polycrystalline silicon film of this invention. In this case, the conventional high-concentration implantation is not required, since a relatively low impurity concentration can provide sufficient activation, resulting in a low resistivity. This prevents accelerated diffusion which is a problem in impurity implantation at high concentration, thereby making it easy to generate a shallow junction.
In general, in fabrication of the dual-gate-structure CMOS transistor, ion implantation into the gate electrode and ion implantation into the source/drain regions are simultaneously carried out so as to reduce the number of fabrication steps. Conventionally, to achieve the above-described simultaneous implantation in the stacking-structure source/drain regions, conditions for the implantation and diffusion (activation) should satisfy the following three conditions: a condition for preventing the gate depletion; a condition for preventing the impurities penetrating from the gate electrode into the channel region; and a condition for preventing the formation of a deep source/drain junctions by impurities expanding into the semiconductor substrate, thereby reducing the effective channel length. In this case, as described above, there is a trade-off relationship between prevention of the gate depletion and prevention of penetration of the impurities into the channel region. Similarly, there is a trade-off relationship between the condition for forming the non-offset source/drain regions and the condition for prevention of penetration of the impurities into the channel region. In the conventional technology, it is difficult to provide conditions satisfying the above-described three conditions simultaneously, resulting in a small process margin.
On the other hand, in this invention, it is possible to improve the activation ratio in the polycrystalline silicon film. Therefore, a small amount of implantation can provide a low resistivity and a low concentration of implantation. As a result, according to this invention, the process margin can be enlarged, so that the above-described three conditions can be easily satisfied.
The source/drain regions, which are stacked above the channel region in the insulating-gate field effect transistor, can include a multilayer film of the polycrystalline silicon film obtained by this invention and a metal film or metal silicide film, thereby obtaining a further low resistivity.
Hereinafter, the functions of this invention will be described.
According to this invention, a reduced crystal defect density (e.g., about 1xc3x971018 cmxe2x88x923 or less) of a polycrystalline semiconductor film (e.g., a polycrystalline silicon film) allows sufficient activation of the impurities therein. As a result, a semiconductor device (e.g., a transistor) having an excellent operating characteristic (e.g., sufficiently high transconductance).
Specifically, there is substantially no depletion of the gate electrode in a transistor including a gate electrode including the polycrystalline semiconductor film (e.g., the polycrystalline silicon film) of this invention. For this reason, there is substantially no variation in threshold voltage and there is a reduction in transistor current in operation. Furthermore, the step for obtaining the low resistivity of the gate and the formation of the source/drain regions can be simultaneously carried out, thereby simplifying the fabricating process.
In a transistor having the stacking structure, the source/drain regions, which are formed of the polycrystalline semiconductor film (e.g., the polycrystalline silicon film) of this invention, can have a low resistivity and a shallow junction simultaneously.
Thus, the invention described herein makes possible the advantages of (1) providing a semiconductor device obtaining a satisfactory characteristic by reducing a crystalline defect density in the polycrystalline semiconductor film constituting the gate electrode or the source/drain regions and therefore increasing an activation ratio of impurities; and (2) providing a method for fabricating the semiconductor device by annealing which allows a significant reduction in crystalline defect density of the polycrystalline semiconductor film.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.